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typical connection high and low side driver features ? floating channel designed for bootstrap operation ? fully operational to +600 v ? tolerant to negative transient voltage, dv/dt immune ? gate drive supply range from 10 v to 20 v ? undervoltage lockout for both channels ? 3.3 v, 5 v, and 15 v input logic compatible ? matched propagation delay for both channels ? logic and power ground +/- 5 v offset. ? lower di/dt gate driver for better noise immunity ? outputs in phase with inputs (irs2106) packages 14-lead soic irs2106/irs21064(s)pbf www.irf.com 1 data sheet no. pd60246 revb (refer to lead assignments for correct pin configuration). these diagrams show electri- cal connections only. please refer to our application notes and designtips for proper circuit board layout. description the irs2106/irs21064 are high voltage, high speed power mosfet and igbt drivers with independent high and low side referenced output channels. proprietary hvic and latch immune cmos technologies enable ruggedized monolithic con- struction. the logic input is compatible with standard cmos or lsttl output, down to 3.3 v logic. irs2106 irs21064 the output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. the floating channel can be used to drive an n-channel power mosfet or igbt in the high side configuration which operates up to 600 v. preliminary 14-lead pdip 8-lead pdip 8-lead soic 220/200 feature comparison
preliminary irs2106/irs21064(s)pbf www.irf.com 2 symbol definition min. max. units v b high side floating absolute voltage -0.3 625 v s high side floating supply offset voltage v b - 25 v b + 0.3 v ho high side floating output voltage v s - 0.3 v b + 0.3 v cc low side and logic fixed supply voltage -0.3 25 v lo low side output voltage -0.3 v cc + 0.3 v in logic input voltage v ss - 0.3 v cc + 0.3 v ss logic ground (irs21064 only) v cc - 25 v cc + 0.3 dv s /dt allowable offset supply voltage transient ? 50 v/ns (8 lead pdip) ? 1.0 p d package power dissipation @ t a +25 c (8 lead soi c) ? 0.625 (14 lead pdip) ? 1.6 (14 lead soic) ? 1.0 (8 lead pdip) ? 125 rth ja thermal resistance, junction to ambient (8 lead soic) ? 200 (14 lead pdip) ? 75 (14 lead soic) ? 120 t j junction temperature ? 150 t s storage temperature -50 150 t l lead temperature (soldering, 10 seconds) ? 300 absolute maximum ratings absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. all voltage param- eters are absolute voltages referenced to com. the thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. v c c/w w
irs2106/irs21064(s)pbf www.irf.com 3 preliminary dynamic electrical characteristics v bias (v cc , v bs ) = 15 v, v ss = com, c l = 1000 pf, t a = 25 c. symbol definition min. typ. max. units test conditions t on turn-on propagation delay ? 220 300 v s = 0 v t off turn-off propagation delay ? 200 280 v s = 0 v or 600 v mt delay matching, hs & ls turn-on/off ? 0 30 t r turn-on rise time ? 100 220 t f turn-off fall time ? 35 80 ns note 1: logic operational for v s of -5 v to +600 v. logic state held for v s of -5 v to -v bs . (please refer to the design tip dt97-3 for more details). vb high side floating supply absolute voltage v s + 10 v s + 20 v s high side floating supply offset voltage note 1 600 v ho high side floating output voltage v s v b v cc low side and logic fixed supply voltage 10 20 v lo low side output voltage 0 v cc v in logic input voltage v ss v cc v ss logic ground (irs21064 only) -5 5 t a ambient temperature -40 125 c v symbol definition min. max. units recommended operating conditions the input/output logic timing diagram is shown in fig. 1. for proper operation the device should be used within the recommended conditions. the v s and v ss offset rating are tested with all supplies biased at a 15 v differential. v s = 0 v
preliminary irs2106/irs21064(s)pbf www.irf.com 4 static electrical characteristics v bias (v cc , v bs ) = 15 v, v ss = com and t a = 25 c unless otherwise specified. the v il , v ih, and i in parameters are referenced to v ss /com and are applicable to the respec tive input leads. the v o , i o, and r on parameters are referenced to com and are applicable to the respective output leads: ho and lo. symbol definition min. typ. max. units test conditions v ih logic 1 input voltage 2.5 v il logic 0 input voltage 0.8 v oh high level output voltage, v bias - v o 0.05 0.2 v ol low level output voltage, v o 0.02 0.1 i lk offset supply leakage current 50 v b = v s = 600 v i qbs quiescent v bs supply current 20 75 130 i qcc quiescent v cc supply current 60 120 180 i in+ logic 1 input bias current v in = 5 v 5 20 i in- logic 0 input bias current v in = 0 v 2 v ccuv+ v cc and v bs supply undervoltage positive going 8.0 8.9 9.8 v bsuv+ threshold v ccuv- v cc and v bs supply undervoltage negative going 7.4 8.2 9.0 v bsuv- threshold v ccuvh hysteresis 0.3 0.7 v bsuvh i o+ output high short circuit pulsed current 130 290 v o = 0 v, pw 10 s i o- output low short circuit pulsed current 270 600 v o = 15 v, pw 10 s v a v v cc = 10 v to 20 v i o = 2 ma v in = 0 v or 5 v ma
irs2106/irs21064(s)pbf www.irf.com 5 preliminary functional block diagrams irs2106 lin uv detect delay com lo vcc hin vs ho vb pulse filter hv level shifter r r s q uv detect pulse generator vss/com level shift vss/com level shift irs21064 lin uv detect delay com lo vcc hin vss vs ho vb pulse filter hv level shifter r r s q uv detect pulse generator vss/com level shift vss/com level shift
preliminary irs2106/irs21064(s)pbf www.irf.com 6 14 lead pdip 14 lead soic irs21064pbf IRS21064SPBF lead assignments 8 lead pdip 8 lead soic lead definitions symbol description hin logic input for high side gate driver output (ho), in phase lin logic input for low side gate driver output (lo), in phase vss logic ground (irs21064 only) v b high side floating supply ho high side gate drive output v s high side floating supply return v cc low side and logic fixed supply lo low side gate drive output com low side return irs2106pbf irs2106spbf 1 2 3 4 8 7 6 5 v cc hin lin com v b ho v s lo 1 2 3 4 8 7 6 5 v cc hin lin com v b ho v s lo 1 2 3 4 5 6 7 1 4 13 12 11 10 9 8 v cc hin lin vss com lo v b ho v s 1 2 3 4 5 6 7 1 4 13 12 11 10 9 8 v cc hin lin vss com lo v b ho v s
irs2106/irs21064(s)pbf www.irf.com 7 preliminary figure 3. delay matching waveform definitions hin lin ho 50% 50% 10% lo 90% mt ho lo mt figure 1. input/output timing diagram hin lin ho lo figure 2. switching time waveform definitions hin lin t r t on t f t off ho lo 50% 50% 90% 90% 10% 10%
preliminary irs2106/irs21064(s)pbf www.irf.com 8 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 temperature ( o c) turn-on propagation delay (ns) typ. max 0 100 200 300 400 500 10 12 14 16 18 20 v bias supply voltage (v) turn-on propagation delay (ns) typ. max. 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 temperature ( o c) turn-off propagation delay (ns) max. typ. 0 100 200 300 400 500 10 12 14 16 18 20 v bias supply voltage (v) turn-off propagation delay (ns) typ. max. figure 4a. turn-on propagation delay vs. temperature figure 4b. turn-on propagation delay vs. supply voltage figure 5a. turn-off propagation delay vs. temperature figure 5b. turn-off propagation delay vs. supply volta ge
irs2106/irs21064(s)pbf www.irf.com 9 preliminary figure 6a. turn-on rise time vs. temperature figure 6b. turn-on rise time vs. supply voltage figure 7a. turn-off fall time vs. temperature figure 7b. turn-off fall time vs. supply volta ge 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 temperature ( o c) t ur n- o n r is e t im e ( n s ) 0 100 200 300 400 500 10 12 14 16 18 20 v bias supply voltage (v) t ur n - o n r is e t im e ( n s ) max. max. typ. typ. 0 50 100 150 200 -50 -25 0 25 50 75 100 125 temperature ( o c) t ur n- o ff f all t im e 0 50 100 150 200 10 12 14 16 18 20 input voltage (v) t ur n- o ff f all t im e typ. max. typ. max. pdf created with pdffactory trial version www.pdffactory.com
preliminary irs2106/irs21064(s)pbf www.irf.com 10 0.0 0.8 1.6 2.4 3.2 4.0 -50 -25 0 25 50 75 100 125 temperature ( o c) i n p u t v o l t a g e ( v ) figure 9a. logic "0" input voltage min. 0.0 0.8 1.6 2.4 3.2 4.0 10 12 14 16 18 20 v cc supply voltage (v) i n p u t v o l t a g e ( v ) min. figure 8a. logic ?1? input voltage vs. temperature figure 8b. logic ?1? input voltage vs. supply voltage figure 9a. logic ?0? input voltage vs. temperature figure 9b. logic ?0? input voltage vs. supply volta ge 0 1 2 3 4 5 6 7 8 10 12 14 16 18 20 v bais supply voltage (v) i n p u t v o l t a g e ( v ) 0 1 2 3 4 5 6 7 8 -50 -25 0 25 50 75 100 125 temperature ( o c) i n p u t v o l t a g e ( v ) min. min. pdf created with pdffactory trial version www.pdffactory.com
irs2106/irs21064(s)pbf www.irf.com 11 preliminary figure 10a. high level output voltage vs. temperature figure 10b. high level output voltage vs. supply voltage figure 11a. low level output voltage vs. temperature figure 11b. low level output voltage vs. supply volta ge 0.0 0.1 0.2 0.3 0.4 0.5 10 12 14 16 18 20 v bais supply voltage (v) high level output voltage (v) 0.0 0.1 0.2 0.3 0.4 0.5 -50 -25 0 25 50 75 100 125 temperature ( o c) high level output voltage (v) 0.0 0.1 0.2 0.3 0.4 0.5 -50 -25 0 25 50 75 100 125 temperature ( o c) low level output voltage (v) 0 0.1 0.2 0.3 0.4 0.5 10 12 14 16 18 20 v bias supply voltage (v) low level output voltage (v) max. typ. max. typ. max. typ. max. typ. high level output voltage (v) high level output voltage (v) low level output voltage (v) low level output voltage (v)
preliminary irs2106/irs21064(s)pbf www.irf.com 12 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 temperature ( o c) offset supply leakage current (ma) max. 0 100 200 300 400 500 0 100 200 300 400 500 600 v b boost voltage (v) offset supply leakage current ( m a) max. 0 100 200 300 400 -50 -25 0 25 50 75 100 125 temperature ( o c) v bs supply current ( m a) typ. max. mi n. 0 100 200 300 400 10 12 14 16 18 20 v bs supply voltage (v) v bs supply current ( m a) typ. max. mi n. figure 12a. offset supply leakage current vs. temperature figure 12b. offset supply leakage current vs. supply voltage figure 13a. v bs supply current vs. temperature figure 13b. v bs supply current vs. supply volta ge
irs2106/irs21064(s)pbf www.irf.com 13 preliminary 0 100 200 300 400 10 12 14 16 18 20 v cc supply voltage (v) v cc supply current ( m a) max. typ. mi n. 0 10 20 30 40 50 60 -50 -25 0 25 50 75 100 125 temperature ( o c) logic "1" input current ( m a) typ. max. 0 10 20 30 40 50 60 10 12 14 16 18 20 v cc supply voltage (v) logic "1" input current ( m a) max. typ. figure 14a. quiescent v cc supply current vs. temperature figure 14b. quiescent v cc supply current vs. v cc supply voltage figure 15a. logic ?1? input current vs. temperature figure 15b. logic ?1? bias current vs. supply volta ge 0 100 200 300 400 - 5 0 - 25 0 2 5 5 0 7 5 100 125 temperature ( o c) vcc supply current ( m a ) m ax. typ. mi n.
preliminary irs2106/irs21064(s)pbf www.irf.com 14 0 1 2 3 4 5 -50 -25 0 25 50 75 100 125 temperature ( o c) logic "0" input current ( m a) m ax. 0 1 2 3 4 5 10 12 14 16 18 20 v cc supply voltage (v) logic "0" input current ( m a) max. 7 8 9 10 11 12 -50 -25 0 25 50 75 100 125 temperature ( o c) v cc uvlo threshold (+) (v) typ. max. mi n. 6 7 8 9 10 11 -50 -25 0 25 50 75 100 125 temperature ( o c) v cc uvlo threshold (-) (v) typ. m ax. mi n. figure 16a. logic ?0? input current vs. temperature figure 16b. logic ?0? input currentt vs. supply voltage figure 17. v cc undervoltage threshold (+) vs. temperature figure 18. v cc undervoltage threshold (-) vs. temperature
irs2106/irs21064(s)pbf www.irf.com 15 preliminary 7 8 9 10 11 12 -50 -25 0 25 50 75 100 125 temperature ( o c) v bs uvlo threshold (+) (v) typ. max. mi n. 6 7 8 9 10 11 -50 -25 0 25 50 75 100 125 temperature ( o c) v bs uvlo threshold (-) (v) typ. max. mi n. figure 19. v bs undervoltage threshold (+) vs. temperature figure 20. v bs undervoltage threshold (-) vs. temperature figure 21a. output source current vs. temperature figure 21b. output source current vs. supply volta ge 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 temperature ( o c) output source current (ma) 0 100 200 300 400 500 10 12 14 16 18 20 v bias supply voltage (v) output source current(ma) max. typ. max. typ.
preliminary irs2106/irs21064(s)pbf www.irf.com 16 1 6 1 1 1 16 1 oaippyoa ffppyoa typ. figure 22a. output sink current vs. temperature figure 22b. output sink currentt vs. supply voltage figure 23. maximum v s negative offset vs. supply voltage 20 40 60 0 100 120 140 1 10 100 1000 frequency (k) temprature ( o c) 0v 140v 0v figure 24. irs2106 vs. frequency (irfbc20), rgate=33 ? ? ? ? ? , vcc=15 v 0 200 400 600 00 1000 50 25 0 25 50 5 100 125 temperature ( o c) output sink current (ma) 0 200 400 600 00 1000 10 12 14 16 1 20 v bias supply voltage (v) output sink current (ma) max. typ. max. typ.
irs2106/irs21064(s)pbf www.irf.com 17 1 1 1 1 1 1 1 rc mrr o 1 7 ir .1.r c 1 ? ? ? ?
preliminary irs2106/irs21064(s)pbf www.irf.com 18 20 0 0 80 100 120 10 1 10 100 1000 rc mrr o 10 0 0 ir 0.210 .r c0 1 1 20 0 0 80 100 120 10 1 10 100 1000 rc mrr o 10 0 0 ir 29.210 .r c0 22 1 20 0 0 80 100 120 10 1 10 100 1000 rc mrr o 0 0 ir 1.210 .r c0 10 1 10 20 0 0 80 100 120 10 1 10 100 1000 rc mrr o ir2.210.rc20 1 0 0 10
irs2106/irs21064(s)pbf www.irf.com 19 preliminary 20 40 60 80 100 120 140 1 10 100 1000 frequency (khz) temperature ( o c) 0v figure 34. irs2106s vs. frequency (irfbc40), r gate =15 , v cc =15 v 140v 70v 20 40 60 80 100 120 140 1 10 100 1000 frequency (khz) temperature ( o c) 140v 70v 0v figure 33. irs2106s vs. frequency (irfbc30), r gate =22 , v cc =15 v 20 40 60 80 100 120 140 1 10 100 1000 frequency (khz) tempreture ( o c) figure 35. irs2106s vs . fre que ncy (irfpe50), r gate =10 , v cc =15 v 140v 70v 0v 20 40 60 80 100 120 140 1 10 100 1000 frequency (khz) temperature ( o c) 140v 70v 0v figure 36. irs21064s vs. frequency (irfbc20), r gate =33 , v cc =15 v
preliminary irs2106/irs21064(s)pbf www.irf.com 20 20 40 60 80 100 120 140 1 10 100 1000 frequency (khz) temperature ( o c) figure 39. irs21064s vs . fre quency (irfpe50), r gate =10 , v cc =15 v 140v 70v 0v 20 40 60 80 10 0 12 0 14 0 1 10 100 1000 frequency (khz) 140v 70v 0v figure 37. irs21064s vs. freque ncy (irfbc30), r g ate =22 , v cc =15 v 20 40 60 80 100 120 140 1 10 100 1000 frequency (khz) temperature ( o c) 140v 70v 0v figure 38. irs21064s vs. frequency (irfbc40), r gate =15 , v cc =15 v temperature ( o c) 140v 70v 0v figure 38. irs21064s vs. frequency (irfbc40), r gate =15 , v cc =15 v
irs2106/irs21064(s)pbf www.irf.com 21 ma case outlines 01-6014 01-3003 01 (ms-001ab) 8 lead pdip 01-6027 01-0021 11 (ms-012aa) 8 lead soic 87 5 65 d b e a e 6x h 0.25 [.010] a 6 4 3 12 4. outline conforms to jedec outline ms-012aa. notes: 1. dimensioning & toleranc ing per asme y14.5m-1994. 2. controlling dimension: millimeter 3. dimensions are shown in millimeters [inches]. 7 k x 45 8x l 8x c y footprint 8x 0.72 [.028] 6.46 [.255] 3x 1.27 [.050] 8x 1.78 [.070] 5 dimension does not include mold protrusions. 6 dimension does not include mold protrusions. mold protrusions not to exc eed 0.25 [.010]. 7 dimension is the length of lead for soldering to a substrate. mold protrusions not to exc eed 0.15 [.006]. 0.25 [.010] cab e1 a a1 8x b c 0.10 [.004] e1 d e y b a a1 h k l .189 .1497 0 .013 .050 basic .0532 .0040 .2284 .0099 .016 .1968 .1574 8 .020 .0688 .0098 .2440 .0196 .050 4.80 3.80 0.33 1.35 0.10 5.80 0.25 0.40 0 1.27 basic 5.00 4.00 0.51 1.75 0.25 6.20 0.50 1.27 min max millimeters in c h e s min max dim 8 e c .0075 .0098 0.19 0.25 .025 basic 0.635 basic
preliminary irs2106/irs21064(s)pbf www.irf.com 22 01-6010 01-3002 03 (ms-001ac) 14 lead pdip 01-6019 01-3063 00 (ms-012ab) 14 lead soic (narrow body)
irs2106/irs21064(s)pbf www.irf.com 23 ma ca a ms sc co mi m mi m a 7 .9 0 .1 0 0. 31 1 0 .3 1 b 3.90 4.10 0.13 0.161 c 11.70 12.30 0.46 0.44 .4 . 0. 21 4 0 .2 1 6 .3 0 6. 0 0. 24 0 .2 .1 0 .3 0 0. 20 0 0 .2 0 1 . 0 0.09 1 . 0 1.6 0 0. 0 9 0 .0 62 m r ic m ri mss sc co mi m mi m a 329.60 330.2 12.976 13.001 b 20.9 21.4 0.24 0.44 c 12.0 13.20 0.03 0.19 1 .9 2.4 0. 76 7 0 .0 96 9.00 102.00 3. 4.01 1.40 0.724 14.0 17.10 0.70 0.673 12.40 14.40 0.4 0.66 m r ic m ri a c a b c ms mm a a c a b c - sc
preliminary irs2106/irs21064(s)pbf www.irf.com 24 carrier tape dimension for 14soicn code min max min max a 7 .9 0 8.1 0 0. 31 1 0 .3 18 b 3.90 4.10 0.153 0.161 c 15.70 16.30 0.618 0.641 d 7 .4 0 7.6 0 0. 29 1 0 .2 99 e 6 .4 0 6.6 0 0. 25 2 0 .2 60 f 9 .4 0 9.6 0 0. 37 0 0 .3 78 g 1 .5 0 n/a 0.059 n/a h 1 .5 0 1.6 0 0. 05 9 0 .0 62 m etr ic im p erial reel d im ension s for 14so ic n code min max min max a 329.60 330.25 12.976 13.001 b 20.95 21.45 0.824 0.844 c 12.80 13.20 0.503 0.519 d 1 .9 5 2.4 5 0. 76 7 0 .0 96 e 98.00 102.00 3.858 4.015 f n/a 22.40 n/a 0.881 g 18.50 21.10 0.728 0.830 h 16.40 18.40 0.645 0.724 m etr ic im p erial e f a c d g a b h n ot e : co ntrolling d imension in mm load ed ta pe feed direction a h f e g d b c tape & reel 14-lead soic
irs2106/irs21064(s)pbf www.irf.com 25 preliminary order information 8-lead pdip irs2106pbf 14-lead pdip irs21064pbf 8-lead soic irs2106spbf 14-lead soic IRS21064SPBF 8-lead soic tape & reel irs2106strpbf 14-lead soic tape & reel irs21064strpbf ir world headquarters: 233 kansas st., el segundo, california 90245 tel: (310) 252-7105 this product has been qualified per industrial level data and specifications subject to change without notice. 5/ /2006 leadfree part marking information lead free released non-lead free released part number date code irxxxxxx yww? ?xxxx pin 1 identifier ir logo lot code (prod mode - 4 digit spn code) assembly site code per scop 200-002 p ? marking code s

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